1. Field of the Disclosure
The present disclosure relates to a display device, and more particularly, to a display device and a method of driving the same.
2. Discussion of the Related Art
With the advancement of information society, demand for a display device capable of displaying an image has increased in various forms. Recently, various flat panel display devices, such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display, have been used.
An OLED display emits light using organic materials radiating red, green and blue, and includes a display panel and a driving circuit.
The OLED display can be manufactured with simpler processes and lower cost than the LCD.
FIG. 1 is a circuit diagram of a pixel of an OLED display according to the related art, and FIG. 2 is a timing chart of control signals of the OLED display according to the related art.
Referring to FIG. 1, the pixel includes first to fourth switching elements S1 to S4, first and second capacitors C1 and C2, and an organic light emitting diode OLED.
The first to fourth switching elements S1 to S4 may be PMOS type transistors.
Source and gate electrodes of the first switching element S1 are supplied with a data signal Data and a select signal Select, respectively, and a drain electrode of the first switching element S1 is connected to an electrode of the first capacitor C1.
Source and gate electrodes of the second switching element S2 are connected to an electrode of the second capacitor C2 and the other electrode of the first capacitor C1, and a drain electrode of the second switching element S2 is connected to a drain electrode of the third switching element S3.
When the second switching element S2 is turned on, a current flows to the organic light emitting diode OLED and the organic light emitting diode OLED emits thus light. The second switching element S2 is referred to as a driving transistor.
A source electrode of the third switching element S3 is connected to the other electrode of the second capacitor C2, a gate electrode of the third switching element S3 is supplied with a control signal Control, and a drain electrode of the third switching element S3 is connected to a source electrode of the fourth switching element S4.
A source electrode of the fourth switching element S4 is connected to the drain electrode of the third switching element S3, a gate electrode of the fourth switching element S4 is supplied with a light emission control signal Em, and a drain electrode of the fourth switching element S4 is connected to an electrode of the organic light emitting diode OLED.
A light intensity of the organic light emitting diode is proportional to an amount of a current flowing thereto, and the amount of the current is proportional to an amplitude of the data signal Data applied to the gate electrode of the driving transistor S2.
Accordingly, various gray levels are shown with various amplitudes of the data signals Data, and images can be displayed.
The pixel is operated using a plurality of control signals, for example, the control signal Control, the light emission control signal Em, the select signal Select, and the like.
Referring to FIG. 2, the data signal Data, the control signal Control and the select signal Select are each a pulse signal which has a low level for a short time and a high level for the remaining long time.
Accordingly, the first and second switching elements S1 and S2 are turned on during a short time the low level is applied.
However, the light emission control signal Em is a pulse signal which has a high level for a short time and a low level for the remaining long time.
Accordingly, the fourth switching element S4 is turned on while a long time the low level is applied.
In case of the first to fourth switching elements S1 to S4 using NMOS type transistors, control signals having the opposite waveform are used.
A control signal circuit generating the control signals is explained as below.
FIG. 3 is a view illustrating a driving unit of a control signal circuit according to the related art, FIG. 4 is a timing chart of a clock signal and an output pulse of a Q node at the driving unit of the control signal circuit according to the related art, and FIG. 5 is a view timing chart of an output pulse at the driving unit of the control signal circuit according to the related art.
Referring to FIG. 3, the control signal circuit includes a plurality of control units 50.
The control unit 50 includes first and second transistors T1 and T2, and outputs an output pulse OUTPUT using a clock signal CLK and the like supplied from a timing control portion and the like.
The first and second transistors T1 and T2 may be PMOS type transistors.
The output pulse OUTPUT from each driving unit 50 is supplied to a switching element of a pixel and controls tuning-on/off the switching element.
The driving unit 50 functions to transfer the clock signal CLK to an output node N according to a Q signal and a Qb signal, which are voltages at Q node and Qb node, respectively.
Accordingly, the output pulse OUTPUT has the same waveform as the clock signal CLK.
However, the output pulse OUTPUT may be deformed at a certain time, which is explained with reference to FIG. 4.
Referring to FIG. 4, for a first time t1, the clock signal CLK maintains a low level, and the Q signal changes from a high level to a low level by a previous output pulse.
The previous output pulse may be a output pulse from a previous driving unit 50.
For a second time t2, the Q signal maintains a low level, and the clock signal CLK changes from a low level to a high level.
Accordingly, for the second time t2, the first transistor T1 is turned on and transfers the clock signal having a high level to the output node N, and the output pulse OUTPUT is output.
However, for the first time t1, the clock signal CLK has a low level, thus a Vgs (i.e., a voltage difference between gate and source electrodes) of the first transistor T1 becomes 0V, and thus the first transistor T1 is turned off. At the same time, the Qb node has a high level, and thus the second transistor T2 is also turned off. Accordingly, the output node N has an electrically floating state.
In other words, when the clock signal CLK and the Q signal have a low level at the same time, the Vgs of the is 0V, and the first transistor T1 is thus turned off, and at the same time, the Qb node is high level, and the second transistor is thus turned off, and finally, the output node N has a floating state.
As a result, referring to FIG. 5, the output pulse OUTPUT is deformed for the first time t1, and an abnormal output is caused as shown in a “B.”